Invention Grant
- Patent Title: Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
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Application No.: US15675001Application Date: 2017-08-11
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Publication No.: US10083855B2Publication Date: 2018-09-25
- Inventor: Igor Peidous , Illaria Katia Marianna Pellicano
- Applicant: SunEdison Semiconductor Limited (UEN201334164H)
- Applicant Address: TW Hsinchu
- Assignee: GlobalWafers Co., Ltd.
- Current Assignee: GlobalWafers Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Armstrong Teasdale LLP
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/02

Abstract:
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
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