Invention Grant
- Patent Title: Vertical transistors having different gate lengths
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Application No.: US15433537Application Date: 2017-02-15
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Publication No.: US10083875B2Publication Date: 2018-09-25
- Inventor: Karthik Balakrishnan , Pouya Hashemi , Tak H. Ning , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Louis Percello
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/8234 ; H01L21/28 ; H01L21/3115 ; H01L21/311 ; H01L29/66

Abstract:
A method of forming a semiconductor device and resulting structures having vertical transistors with different gate lengths are provided. A sacrificial gate is formed over a channel region of a semiconductor fin. The sacrificial gate includes a first material. The first material in a first portion of the sacrificial gate adjacent to the semiconductor fin is converted to a second material, the first portion having a first depth. The first portion of the sacrificial gate is then removed.
Public/Granted literature
- US20180076093A1 VERTICAL TRANSISTORS HAVING DIFFERENT GATE LENGTHS Public/Granted day:2018-03-15
Information query
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