Invention Grant
- Patent Title: Semiconductor device and method of forming stress relief layer between die and interconnect structure
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Application No.: US14637054Application Date: 2015-03-03
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Publication No.: US10083916B2Publication Date: 2018-09-25
- Inventor: Il Kwon Shim , Seng Guan Chow , Yaojian Yaojian
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/10 ; H01L21/56 ; H01L21/683 ; H01L23/31 ; H01L23/538 ; H01L23/66

Abstract:
A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.
Public/Granted literature
- US20150179587A1 Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure Public/Granted day:2015-06-25
Information query
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