Invention Grant
- Patent Title: Low warpage wafer bonding through use of slotted substrates
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Application No.: US15438592Application Date: 2017-02-21
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Publication No.: US10084110B2Publication Date: 2018-09-25
- Inventor: Marc Andre De Samber , Eric Cornelis Egbertus Van Grunsven , Roy Antoin Bastiaan Engelen
- Applicant: KONINKLIJKE PHILIPS N.V.
- Applicant Address: NL Eindhoven
- Assignee: Koninklijke Philips N.V.
- Current Assignee: Koninklijke Philips N.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H01L33/00
- IPC: H01L33/00 ; H01L23/00 ; H01L33/12 ; H01L21/768 ; H01L29/06 ; H01L33/62 ; H01L33/48 ; H01L25/075

Abstract:
In a wafer bonding process, one or both of two wafer substrates are scored prior to bonding. By creating slots in the substrate, the wafer's characteristics during bonding are similar to that of a thinner wafer, thereby reducing potential warpage due to differences in CTE characteristics associated with each of the wafers. Preferably, the slots are created consistent with the singulation/dicing pattern, so that the slots will not be present in the singulated packages, thereby retaining the structural characteristics of the full-thickness substrates.
Public/Granted literature
- US20170200853A1 LOW WARPAGE WAFER BONDING THROUGH USE OF SLOTTED SUBSTRATES Public/Granted day:2017-07-13
Information query
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