Invention Grant
- Patent Title: Low-inductance direct current power bus
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Application No.: US15426844Application Date: 2017-02-07
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Publication No.: US10084310B1Publication Date: 2018-09-25
- Inventor: Jason C. Neely , Joshua Stewart , Jarod James Delhotal , Jack David Flicker , Geoff L. Brennecka
- Applicant: Sandia Corporation
- Applicant Address: US NM Albuquerque
- Assignee: National Technology & Engineering Solutions of Sandia, LLC
- Current Assignee: National Technology & Engineering Solutions of Sandia, LLC
- Current Assignee Address: US NM Albuquerque
- Agent Martin I. Finston
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H02J1/02 ; H01L29/16 ; H02M7/00 ; B60L11/18 ; B60R16/03

Abstract:
A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.
Information query
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