An interfacing circuit adaptable to an analog-to-digital converter (ADC) includes a sample and hold (S/H) circuit; an input switch; an input capacitor with a first end connected to an input end of a comparator of the ADC via the S/H circuit, and with a second end connected to receive an input signal via the input switch; a hold switch connected between the second end of the input capacitor and an original common-mode voltage; a reset switch connected between the input end of the comparator and a target common-mode voltage; and a front switch connected between the first end of the input capacitor and the target common-mode voltage.