Invention Grant
- Patent Title: Method and apparatus of instruction that merges and sorts smaller sorted vectors into larger sorted vector
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Application No.: US13996972Application Date: 2012-03-30
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Publication No.: US10089075B2Publication Date: 2018-10-02
- Inventor: Jatin Chhugani , Changkyu Ck Kim , Nadathur Rajagopalan Satish
- Applicant: Jatin Chhugani , Nadathur Rajagopalan Satish
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- International Application: PCT/US2012/031645 WO 20120330
- International Announcement: WO2013/147880 WO 20131003
- Main IPC: G06F7/36
- IPC: G06F7/36 ; G06F9/30 ; G06F9/38

Abstract:
A semiconductor chip is described that includes an instruction execution unit having a functional unit, said functional unit having minimum and maximum comparison circuitry followed by interleaving circuitry, said minimum and maximum comparison circuitry to respectively identify minimums and maximums of same positioned elements from two different sets of sorted elements, said interleaving circuitry to interleave said minimums and maximums to help form a third sorted set composed of elements from said different sets and being larger than each of said different sets.
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