Invention Grant
- Patent Title: Chip packaging method and package structure
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Application No.: US15509602Application Date: 2015-09-10
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Publication No.: US10090217B2Publication Date: 2018-10-02
- Inventor: Zhiqi Wang , Qiong Yu , Wei Wang
- Applicant: China Wafer Level CSP Co., Ltd.
- Applicant Address: CN Suzhou, Jiangsu
- Assignee: China Wafer Level CSP Co., Ltd.
- Current Assignee: China Wafer Level CSP Co., Ltd.
- Current Assignee Address: CN Suzhou, Jiangsu
- Agency: Wolf, Greenfield & Sacks, P.C.
- Priority: CN201410465882 20140912
- International Application: PCT/CN2015/089304 WO 20150910
- International Announcement: WO2016/037574 WO 20160317
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/08 ; H01L23/04 ; H01L23/498 ; H01L23/58 ; H01L23/29 ; G06K9/00 ; H01L23/31 ; H01L23/00

Abstract:
A chip packaging method and package structure, the package structure including a substrate, a sensing chip coupled to the substrate, a plastic package layer located on the substrate, and a covering layer located on the plastic package layer and a first surface of the sensing chip; the sensing chip including the first surface and a second surface opposite to the first surface, and further including a sensing area located on the first surface; the second surface of the sensing chip faces towards the substrate; and the plastic package layer encloses the sensing chip, and the surface of the plastic package layer is flush with the first surface of the sensing chip.
Public/Granted literature
- US20170287797A1 CHIP PACKAGING METHOD AND PACKAGE STRUCTURE Public/Granted day:2017-10-05
Information query
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