A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, and generating an up/down signal according to the lengths of a second section of the target clock and the first section of the selected delayed clock, a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal, a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock, and a control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction period.