A memory controller 2 of a memory system 1 according to an embodiment is provided with an encoding device 10 and a memory interface 5. The encoding device 10 is provided with an encoder 15 which generates a plurality of first parities by encoding a plurality of user data by using a common code, an interleaver 111 which sequentially interleaves the plurality of user data, and an XOR accumulator 112 which sequentially executes component-wise modulo-2 operation on the interleaved plurality of user data. The encoder 15 generates second parity by encoding a result finally obtained by executing the component-wise modulo-2 operation on a plurality of user data. The memory interface 5 writes a code word sequence including the plurality of user data, the first parities and the second parity in a non-volatile memory 9.