Invention Grant
- Patent Title: Test circuit for 3D semiconductor device and method for testing thereof
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Application No.: US15291172Application Date: 2016-10-12
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Publication No.: US10095591B2Publication Date: 2018-10-09
- Inventor: Sung Ho Kang , In Geol Lee
- Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
- Applicant Address: KR Seoul
- Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
- Current Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
- Current Assignee Address: KR Seoul
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2016-0046987 20160418
- Main IPC: G06F11/16
- IPC: G06F11/16 ; G01R31/317 ; G11C29/40 ; G01R31/3181 ; G01R31/3185 ; G01R31/3183

Abstract:
Disclosed herein is a test circuit for a 3D semiconductor device for detecting soft errors and a method for testing thereof. The test circuit includes a first Multiple Input Signature Register (MISR) disposed in a first semiconductor chip, the first MISR compressing a first test result signal corresponding to a test pattern, a second MISR disposed in a second semiconductor chip stacked on or under the first semiconductor chip, the second MISR compressing a second test result signal corresponding to the test pattern, and a first error detector to detect a soft error by comparing a first output signal output from the first MISR with a second output signal output from the second MISR.
Public/Granted literature
- US20170300392A1 TEST CIRCUIT FOR 3D SEMICONDUCTOR DEVICE AND METHOD FOR TESTING THEREOF Public/Granted day:2017-10-19
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