A semiconductor storage device according to one embodiment includes a memory cell. A first latch is selectively coupled to the memory cell. A first bus coupled to the first latch and a second latch. A first charger charges the first bus. A second bus transmits a signal of the same value both when first data is output and when second data is output from the first or second latch A second charger raises a voltage of the second bus from a first value to a second value. A controller whose input is coupled to the second bus controls the first charger to stop charging of the first bus based on the voltage of the second bus having reached the second value.