Invention Grant
- Patent Title: Packing method for semiconductor device
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Application No.: US15489775Application Date: 2017-04-18
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Publication No.: US10103036B2Publication Date: 2018-10-16
- Inventor: Hiroaki Tanoue , Kei Goto
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP2016-129848 20160630
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/31 ; H01L23/495

Abstract:
A packing method for a semiconductor device includes a step of preparing the semiconductor device that has a sealing body having a principal surface and a plurality of leads, and a step of preparing a base carrier tape that has a peripheral portion, a step portion, and a pocket portion. The method further includes a step of placing the semiconductor device in the pocket portion, a step of bonding a cover tape to the step portion in such a manner that the sealing body is pressed against the base carrier tape, and a step of winding the base carrier tape with the semiconductor device placed therein and with the cover tape bonded thereto, around a tape reel. The base carrier tape includes a principal surface of the peripheral portion, a principal surface of the step portion, and a principal surface of the pocket portion.
Public/Granted literature
- US20180005845A1 PACKING METHOD FOR SEMICONDUCTOR DEVICE Public/Granted day:2018-01-04
Information query
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