Invention Grant
- Patent Title: Method for filling a wafer via with solder
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Application No.: US15423602Application Date: 2017-02-03
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Publication No.: US10115635B2Publication Date: 2018-10-30
- Inventor: Sehoon Yoo , Chang Woo Lee , Jun Ki Kim , Jeong Han Kim , Young Ki Ko
- Applicant: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
- Applicant Address: KR Cheonan
- Assignee: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
- Current Assignee: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
- Current Assignee Address: KR Cheonan
- Agency: Cantor Colburn LLP
- Priority: CN10-2011-0068845 20120710
- Main IPC: B23K1/00
- IPC: B23K1/00 ; H01L21/768 ; H01L23/48 ; B23K3/06 ; B23K1/20 ; B23K3/08 ; B23K101/40
Abstract:
A wafer via solder filling device includes a solder bath comprising an accommodation space for accommodating a molten solder, with an open top, and an air outlet for exhausting air from the accommodation space; a fixing unit for fixing the wafer having a via formed in one surface in the accommodation space to seal the accommodation space airtight; and a pressing unit for pressing a bottom of the molten solder arranged in the solder bath and moving the molten solder upward, to fill the molten solder in the via.
Public/Granted literature
- US20180301377A9 METHOD FOR FILLING A WAFER VIA WITH SOLDER Public/Granted day:2018-10-18
Information query
IPC分类:
