A training controller, semiconductor device and a system including the same are disclosed, which relates to technology for training a phase of data. The training controller may include a read training circuit configured to control a read training operation based on a read signal and a control signal. The training controller may include a write training circuit configured to control a write training operation based on a write signal and a write training signal. The training controller may include a reset controller configured to generate a reset signal when a mismatch occurs in the read training operation or the write training operation.