Invention Grant
- Patent Title: Wafer bonding process and structure
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Application No.: US15238532Application Date: 2016-08-16
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Publication No.: US10128209B2Publication Date: 2018-11-13
- Inventor: Ping-Yin Liu , Lan-Lin Chao , Cheng-Tai Hsiao , Xin-Hua Huang , Hsun-Chung Kuang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/40
- IPC: H01L23/40 ; H01L23/00 ; H01L25/065

Abstract:
A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
Public/Granted literature
- US20160358882A1 Wafer Bonding Process and Structure Public/Granted day:2016-12-08
Information query
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