Invention Grant
- Patent Title: Semiconductor memory with data line capacitive coupling
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Application No.: US15865036Application Date: 2018-01-08
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Publication No.: US10134467B2Publication Date: 2018-11-20
- Inventor: Jhon-Jhy Liaw
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: G11C11/419
- IPC: G11C11/419 ; G11C11/412 ; G11C11/00 ; G11C7/12

Abstract:
A semiconductor memory is disclosed that includes a first data line, a first coupling line, and a second coupling line. The first coupling line is configured to capacitively couple the first coupling line with the first data line. The second coupling line is configured to capacitively couple the second coupling line with the first data line. The first data line and the first coupling line are formed in a first conductive layer, and the second coupling line is formed in a second conductive layer that is different from the first conductive layer.
Public/Granted literature
- US20180130525A1 SEMICONDUCTOR MEMORY WITH DATA LINE CAPACITIVE COUPLING Public/Granted day:2018-05-10
Information query
IPC分类: