Invention Grant
- Patent Title: Low temperature atomic layer deposition of oxides on compound semiconductors
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Application No.: US14830131Application Date: 2015-08-19
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Publication No.: US10134585B2Publication Date: 2018-11-20
- Inventor: Kasra Sardashti , Tobin Kaufman-Osborn , Tyler Kent , Andrew Kummel , Shariq Siddiqui , Bhagawan Sahu , Adam Brand , Naomi Yoshida
- Applicant: The Regents of the University of California , GLOBALFOUNDRIES, Inc. , Applied Materials, Inc.
- Applicant Address: US CA Oakland
- Assignee: The Regents of the University of California
- Current Assignee: The Regents of the University of California
- Current Assignee Address: US CA Oakland
- Agency: Greer, Burns & Crain, Ltd.
- Agent Steven P. Fallon
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/66 ; H01L21/306 ; H01L29/94

Abstract:
Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.
Public/Granted literature
- US20160056033A1 LOW TEMPERATURE ATOMIC LAYER DEPOSITION OF OXIDES ON COMPOUND SEMICONDUCTORS Public/Granted day:2016-02-25
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