Invention Grant
- Patent Title: Reduction of negative bias temperature instability
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Application No.: US14585401Application Date: 2014-12-30
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Publication No.: US10134732B2Publication Date: 2018-11-20
- Inventor: Takashi Ando , Barry P. Linder
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L27/092 ; H01L21/8238 ; H01L29/51 ; H01L21/02 ; H01L21/28 ; H01L29/66 ; H01L27/02

Abstract:
A complementary metal-oxide semiconductor (CMOS) circuit and a method of fabricating the device are described. The circuit includes an n-channel field effect transistor (nFET), the nFET including a high-k dielectric layer on an interlayer. The CMOS circuit also includes a p-channel field effect transistor (pFET), the pFET including the high-k dielectric layer on the interlayer and additionally including an aluminum-based cap layer between the high-k dielectric layer and a pFET work function setting metal. Metal atoms from the cap layer do not intermix with the interlayer.
Public/Granted literature
- US20150287649A1 REDUCTION OF NEGATIVE BIAS TEMPERATURE INSTABILITY Public/Granted day:2015-10-08
Information query
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