Invention Grant
- Patent Title: TSV layout structure and TSV interconnect structure, and fabrication methods thereof
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Application No.: US14181862Application Date: 2014-02-17
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Publication No.: US10141244B2Publication Date: 2018-11-27
- Inventor: Wuzhi Zhang , Xiaojun Chen , Xuanjie Liu , Haifang Zhang
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicant Address: CN Shanghai
- Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee Address: CN Shanghai
- Agency: Anova Law Group, PLLC
- Priority: CN201310106719 20130328
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/48 ; H01L21/768
Abstract:
TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average through-hole density of the first region is greater than an average through-hole density of the entire semiconductor substrate. The average through-hole density of the entire semiconductor substrate is less than or equal to about 2%. A metal layer having a planarized surface is filled in the plurality of through-holes in the semiconductor substrate.
Public/Granted literature
- US20140291856A1 TSV LAYOUT STRUCTURE AND TSV INTERCONNECT STRUCTURE, AND FABRICATION METHODS THEREOF Public/Granted day:2014-10-02
Information query
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