Invention Grant
- Patent Title: Lithography process and system with enhanced overlay quality
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Application No.: US14471653Application Date: 2014-08-28
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Publication No.: US10146141B2Publication Date: 2018-12-04
- Inventor: Chi-Cheng Hung , Wei-Liang Lin , Yung-Sung Yen , Chun-Kuang Chen , Ru-Gun Liu , Tsai-Sheng Gau , Tzung-Chi Fu , Ming-Sen Tung , Fu-Jye Liang , Li-Jui Chen , Meng-Wei Chen , Kuei-Shun Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G03F7/20
- IPC: G03F7/20

Abstract:
The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.
Public/Granted literature
- US20160062250A1 Lithography Process and System with Enhanced Overlay Quality Public/Granted day:2016-03-03
Information query
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