Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.