An array substrate, a method of manufacturing the same, and a display device are provided. In the array substrate of the present disclosure, the gate cutout is formed in the area where the gate line intersects the data line. The array substrate can reduce the coupling capacitance between the data line and the gate line. When the gate cutout extends beyond the area between the first thin film transistor and the second thin film transistor, the mutual interference between two thin film transistors of each pixel region can be further reduced.