Invention Grant
- Patent Title: Transistor with buried P+ and source contact
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Application No.: US13572110Application Date: 2012-08-10
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Publication No.: US10147801B2Publication Date: 2018-12-04
- Inventor: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
- Applicant: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
- Applicant Address: US CA San Jose
- Assignee: Volterra Semiconductor LLC
- Current Assignee: Volterra Semiconductor LLC
- Current Assignee Address: US CA San Jose
- Agency: Lathrop Gage LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L21/8234 ; H01L27/088 ; H01L21/265 ; H01L21/28 ; H01L29/417 ; H01L29/423 ; H01L29/45 ; H01L29/49 ; H01L29/08 ; H01L29/10
Abstract:
The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.
Public/Granted literature
- US20130105888A1 Transistor with Buried P+ and Source Contact Public/Granted day:2013-05-02
Information query
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