- Patent Title: Bit-flipping LDPC decoding algorithm with hard channel information
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Application No.: US15346158Application Date: 2016-11-08
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Publication No.: US10148287B2Publication Date: 2018-12-04
- Inventor: Chenrong Xiong , Fan Zhang , Aman Bhatia , Abhiram Prabhakar , HongChich Chou , Naveen Kumar
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Main IPC: H03M13/11
- IPC: H03M13/11 ; G06F3/06 ; G06F11/10 ; G11C29/52

Abstract:
Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.
Public/Granted literature
- US20180131389A1 BIT-FLIPPING LDPC DECODING ALGORITHM WITH HARD CHANNEL INFORMATION Public/Granted day:2018-05-10
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