A method of fabricating a semiconductor device. The method includes forming source/drain features in a substrate on opposite sides of a gate structure, forming an etch stop layer over the source/drain features, and depositing a dielectric layer on the etch stop layer. The method further includes performing a first atomic layer etching (ALE) process having a first operating parameter value on the dielectric layer to form a first part of an opening, and performing a second ALE process having a second operating parameter value to extend the opening to expose the source/drain features. The first operating parameter value is different from the second operating parameter value.