Invention Grant
- Patent Title: Semiconductor device
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Application No.: US15582983Application Date: 2017-05-01
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Publication No.: US10153274B2Publication Date: 2018-12-11
- Inventor: Sadayuki Ohnishi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP2015-027467 20150216
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L29/735 ; H01L29/06 ; H01L21/8249 ; H01L29/40 ; H01L29/417 ; H01L29/66 ; H01L29/732 ; H01L29/08

Abstract:
A p-type well is formed in a semiconductor substrate, and an n+-type semiconductor region and a p+-type semiconductor region are formed in the p-type well to be spaced apart from each other. The n+-type semiconductor region is an emitter semiconductor region of a bipolar transistor, and the p-type well and the p+-type semiconductor region are base semiconductor regions of the bipolar transistor. An electrode is formed on an element isolation region between the n+-type semiconductor region and the p+-type semiconductor region, and at least apart of the electrode is buried in a trench which is formed in the element isolation region. The electrode is electrically connected to the n+-type semiconductor region.
Public/Granted literature
- US20170236818A1 SEMICONDUCTOR DEVICE Public/Granted day:2017-08-17
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