Invention Grant
- Patent Title: Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis
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Application No.: US14797841Application Date: 2015-07-13
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Publication No.: US10153769B2Publication Date: 2018-12-11
- Inventor: Ozgur Sinanoglu , Youngok Pino , Jeyavijayan Rajendran , Ramesh Karri
- Applicant: New York University
- Applicant Address: US NY New York
- Assignee: New York University
- Current Assignee: New York University
- Current Assignee Address: US NY New York
- Agency: Hunton Andrews Kurth LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K19/003 ; G09C1/00 ; H04L9/08

Abstract:
Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.
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