Invention Grant
- Patent Title: Processing of multiple instruction streams in a parallel slice processor
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Application No.: US15442810Application Date: 2017-02-27
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Publication No.: US10157064B2Publication Date: 2018-12-18
- Inventor: Lee Evan Eisen , Hung Qui Le , Jentje Leenstra , Jose Eduardo Moreira , Bruce Joseph Ronchetti , Brian William Thompto , Albert James Van Norstrand, Jr.
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Mitch Harris, Atty at Law, LLC
- Agent Andrew M. Harris; Steven L. Bennett
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/45 ; G06F9/50 ; G06F15/80 ; G06F9/38 ; G06F9/48

Abstract:
A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream will not be met by the instruction execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.
Public/Granted literature
- US20170168837A1 PROCESSING OF MULTIPLE INSTRUCTION STREAMS IN A PARALLEL SLICE PROCESSOR Public/Granted day:2017-06-15
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