- Patent Title: Interconnect structure including a conductive feature and a barrier layer on sidewalls and a bottom surface of the conductive feature and method of forming the same
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Application No.: US14175685Application Date: 2014-02-07
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Publication No.: US10163644B2Publication Date: 2018-12-25
- Inventor: Rueijer Lin , Ya-Lien Lee , Chun-Chieh Lin , Hung-Wen Su
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/285 ; H01L21/768

Abstract:
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
Public/Granted literature
- US20150228605A1 Interconnect Structure and Method of Forming the Same Public/Granted day:2015-08-13
Information query
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