Invention Grant
- Patent Title: Systems and methods for a sequential spacer scheme
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Application No.: US15668930Application Date: 2017-08-04
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Publication No.: US10163885B2Publication Date: 2018-12-25
- Inventor: Shih-Ming Chang , Ming-Feng Shieh , Ru-Gun Liu , Tsai-Sheng Gau
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L21/768 ; H01L21/3213 ; H01L21/033 ; H01L23/522 ; H01L21/308 ; H01L29/06

Abstract:
Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a target layer disposed over the substrate. The target layer includes a first target feature, a second target feature, and a third target feature. The second target feature is spaced a first distance from the first target feature, and the third target feature is spaced a second distance from the first target feature. The first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process.
Public/Granted literature
- US20170358566A1 Systems and Methods for a Sequential Spacer Scheme Public/Granted day:2017-12-14
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