Invention Grant
- Patent Title: Method for manufacturing semiconductor structure
-
Application No.: US15652176Application Date: 2017-07-17
-
Publication No.: US10164046B2Publication Date: 2018-12-25
- Inventor: Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee Address: TW Hsinchu
- Agency: Cooper Legal Group, LLC
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L29/417 ; H01L29/40 ; H01L21/311 ; H01L29/51 ; H01L29/06

Abstract:
A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.
Public/Granted literature
- US20170317178A1 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE Public/Granted day:2017-11-02
Information query
IPC分类: