The present invention relates to a converter circuit (1) for reducing a nominal capacitor voltage, the converter circuit (1) comprising: an input node (TI1), which is configured to receive an input voltage (VG); an output node (TO1; TO2), which is configured to supply an output voltage (VO) to a load (RL1; RL2); and a capacitor (C1; C2), which is coupled to the load so that the input voltage is divided between the capacitor (C1; C2) and the load (RL1; RL2) and which is configured to be charged up to a voltage corresponding to a differential voltage between the input voltage (VG) and the output voltage (VO).