A digital signal synthesizer for generating a frequency and/or phase modified digital signal output comprises an input buffer, a transform module, a processing module, and an output buffer. The input buffer receives a digital input that is represented in a frequency domain representation. The transform module stores a fractional order control system that models a desired frequency and/or phase response defined by an assembly of at least one filter component. Each filter component is defined by a Laplace function that is modified to include a non-integer control order having a variable fractional scaling exponent. The processing module multiplies or divides the digital input with the fractional order control system stored in the transform module. Moreover, the output buffer stores a synthesized output of the input, which is modified in the frequency domain, the phase domain, or both according to the desired frequency and/or phase response by the processing module.