Invention Grant
- Patent Title: Method for manufacturing multilayer wiring substrate
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Application No.: US15027774Application Date: 2014-09-24
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Publication No.: US10165691B2Publication Date: 2018-12-25
- Inventor: Nobuyuki Yoshida
- Applicant: HITACHI CHEMICAL COMPANY, LTD.
- Applicant Address: JP Tokyo
- Assignee: HITACHI CHEMICAL COMPANY, LTD.
- Current Assignee: HITACHI CHEMICAL COMPANY, LTD.
- Current Assignee Address: JP Tokyo
- Agency: Fitch, Even, Tabin & Flannery, L.L.P.
- Priority: JP2013-211871 20131009; JP2014-147756 20140718
- International Application: PCT/JP2014/075256 WO 20140924
- International Announcement: WO2015/053083 WO 20150416
- Main IPC: H05K3/42
- IPC: H05K3/42 ; H05K3/46 ; H05K3/00

Abstract:
The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole, an overhang of a metal foil formed at an opening of the hole, and lower space formed between the overhang and an inside wall of the hole, by using a conformal method or a direct laser method; and (2) a step of filling in the hole by forming electrolytic filling plating layers within the hole and on the metal foil, wherein the filling-in of the hole by the formation of electrolytic filling plating layers in the step (2) is carried out by temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating, and increasing it again.
Public/Granted literature
- US20160249463A1 METHOD FOR MANUFACTURING MULTILAYER WIRING SUBSTRATE Public/Granted day:2016-08-25
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