Invention Grant
- Patent Title: Efficient validation of transactional memory in a computer processor
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Application No.: US15265939Application Date: 2016-09-15
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Publication No.: US10169181B2Publication Date: 2019-01-01
- Inventor: Vinod Bussa , Manoj Dusanapudi , Shakti Kapoor
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Martin & Associates, LLC
- Agent Bret J. Petersen
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/273 ; G06F11/22 ; G06F11/36 ; G06F11/263 ; G06F11/16

Abstract:
A transactional memory test tests a transactional memory system on a computer processor. A test case with a transactional memory test is constructed such that the transactional memory test proceeds further in the transaction mode if the transaction is successful. In contrast, if there is a failure of the transaction, then the transactional memory test is executed in the non-transaction state. The transactional memory test stresses both transaction success and transaction failure cases of the processor for more efficient validation of the computer processor. Also, when checking the correctness of the test case the correct result remains the same whether the transaction passes or fails to simplify verification.
Public/Granted literature
- US20180074926A1 EFFICIENT VALIDATION OF TRANSACTIONAL MEMORY IN A COMPUTER PROCESSOR Public/Granted day:2018-03-15
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