Invention Grant
- Patent Title: Reducing metadata size in compressed memory systems of processor-based systems
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Application No.: US15592611Application Date: 2017-05-11
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Publication No.: US10169246B2Publication Date: 2019-01-01
- Inventor: Richard Senior , Christopher Edward Koob , Gurvinder Singh Chhabra , Andres Alejandro Oportus Valenzuela , Nieyan Geng , Raghuveer Raghavendra , Christopher Porter , Anand Janakiraman
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/02 ; G06F12/1036

Abstract:
Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.
Public/Granted literature
- US20180329830A1 REDUCING METADATA SIZE IN COMPRESSED MEMORY SYSTEMS OF PROCESSOR-BASED SYSTEMS Public/Granted day:2018-11-15
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