In an approach for addressing process and voltage points across voltage and process space, a computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies a minimum set of voltage/process pairs associated with the integrated circuit design. The computer identifies a number n that defines the number of finite differencing operations to be performed for the identified minimum set of voltage/process pairs. The computer performs a single statistical static timing analysis with multi-corner projection for the identified integrated circuit based on the received number n that provides a finite difference for each number of finite differencing operations to be performed based on n for the identified minimum set of voltage/process pairs. The computer performs addressing based on the performed statistical static timing analysis. The computer provides a report.