Invention Grant
- Patent Title: Partitioning and routing multi-SLR FPGA for emulation and prototyping
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Application No.: US15184266Application Date: 2016-06-16
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Publication No.: US10169505B2Publication Date: 2019-01-01
- Inventor: Etienne Lepercq , Alexander Rabinovitch
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: SYNOPSYS, INC.
- Current Assignee: SYNOPSYS, INC.
- Current Assignee Address: US CA Mountain View
- Agency: Alston & Bird LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A computer-implemented method for configuring a hardware verification system includes receiving, in the computer, a first data representative of a first design. The method further includes performing a first mapping of the first data to generate a second data in accordance with a first cost function and one or more first delays each associated with a different one of a first multitude of paths. One of the first multitude of paths includes a critical path characterized by a second delay. The method further includes performing a second mapping of the second data to generate a third data in accordance with a second cost function and a multitude of third delays each associated with a different one of a second multitude of paths and the second delay. The method further includes compiling the third data for configuring the hardware verification system.
Public/Granted literature
- US20170364621A1 PARTITIONING AND ROUTING MULTI-SLR FPGA FOR EMULATION AND PROTOTYPING Public/Granted day:2017-12-21
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