Invention Grant
- Patent Title: Apparatus and methods of operating memory for negative gate to body conditions
-
Application No.: US15935126Application Date: 2018-03-26
-
Publication No.: US10170193B2Publication Date: 2019-01-01
- Inventor: Toru Tanzawa
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C16/14 ; G11C16/04 ; G11C16/34 ; G11C16/08 ; G11C16/16

Abstract:
Methods of operating a memory, and apparatus so configured, include applying a first voltage level to a first voltage node connected to a first end of a string of series-connected memory cells, applying a second voltage level to a second voltage node connected to a second end of the string, applying a third voltage level less than the first and second voltage levels to a control gate of a first memory cell of the string while applying the first and second voltage levels to the first and second voltage nodes, and applying a fourth voltage level less than the third voltage level to a control gate of a second memory cell of the string while applying the third voltage level to the control gate of the first memory cell, wherein the first memory cell is closer to the first voltage node than the second memory cell.
Public/Granted literature
- US20180211711A1 APPARATUS AND METHODS OF OPERATING MEMORY FOR NEGATIVE GATE TO BODY CONDITIONS Public/Granted day:2018-07-26
Information query