- Patent Title: Method for bonding and interconnecting integrated circuit devices
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Application No.: US15697285Application Date: 2017-09-06
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Publication No.: US10170450B2Publication Date: 2019-01-01
- Inventor: Eric Beyne , Joeri De Vos , Stefaan Van Huylenbroeck
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC vzw
- Current Assignee: IMEC vzw
- Current Assignee Address: BE Leuven
- Agency: Knobbe Martens Olson & Bear LLP
- Priority: EP16187668 20160907
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/768 ; H01L23/00 ; H01L25/00 ; H01L23/48 ; H01L21/3065

Abstract:
A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.
Public/Granted literature
- US20180068984A1 METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES Public/Granted day:2018-03-08
Information query
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