Invention Grant
- Patent Title: Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
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Application No.: US15729002Application Date: 2017-10-10
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Publication No.: US10170476B2Publication Date: 2019-01-01
- Inventor: Phillip F. Chapman , David S. Collins , Steven H. Voldman
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran Cole & Calderon, P.C.
- Agent Steven J. Meyers; Andrew M. Calderon
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/74 ; H01L21/762 ; H01L21/768 ; H01L21/8238 ; H01L23/48 ; H01L29/06
Abstract:
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
Public/Granted literature
- US20180040619A1 STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY Public/Granted day:2018-02-08
Information query
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