Invention Grant
- Patent Title: Uniform bottom spacer for vertical field effect transistor
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Application No.: US15703105Application Date: 2017-09-13
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Publication No.: US10170582B1Publication Date: 2019-01-01
- Inventor: Michael P. Belyansky , Cheng Chi , Ekmini Anuja De Silva , Tenko Yamashita
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Michael A. Petrocelli
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/66 ; H01L29/78 ; H01L21/033 ; H01L21/02

Abstract:
A method of forming a semiconductor structure includes forming a protective liner comprising a metal oxide above and in direct contact with a semiconductor substrate, a fin extending upward from the semiconductor substrate and a NON hardmask positioned on top of the fin, removing the protective liner from top surfaces of the semiconductor substrate and NON hardmask, the protective liner remaining on sidewalls of the fin and the NON hardmask, depositing a first dielectric layer, simultaneously removing top portions of the first dielectric layer and NON hardmask, the first dielectric layer remains in direct contact with a bottom portion of the protective liner and the semiconductor substrate, removing the protective liner, the removing of the protective liner creates an opening between the first dielectric layer and the bottom portion of the fin that is subsequently filled with a second dielectric layer.
Information query
IPC分类: