A PWM signal generation circuit controls a current mode to set a PWM signal to an on-level in synchronization with a dock signal and set the PWM signal to an off-level in synchronization with a normal reset signal, which changes its level when a current detection signal reaches an error signal. A switching determination circuit checks whether an output voltage reached a switching determination voltage higher than a target output voltage. A reset signal generation circuit generates a reset signal, which is delayed by a predetermine time period from a time point of a change of the PWM signal to the on-level. When the switching determination circuit determines that the output voltage reached the switching determination voltage, the PWM signal generation circuit changes the PWM signal to the off-level in synchronization with the reset signal in place of the reset signal.