Provided is a gate driver and a method of driving the same, which enables a voltage level of a Q node to be stably maintained in a blank section by: inputting a clock signal that directly provides a high level to the Q node through a reset signal input end of a reset signal for resetting the Q node of a gate driver integrated circuit; inputting a reset signal for each blank section between frames; or providing a higher gate high voltage and a lower gate low voltage. There may be provided a gate driver integrated circuit that has a robust structure with high reliability and avoids an error of a scan signal by maintaining the voltage level of the Q node to be stable in the blank section, and a method of driving the same.