Invention Grant
- Patent Title: Method of manufacturing semiconductor device
-
Application No.: US15670809Application Date: 2017-08-07
-
Publication No.: US10177035B2Publication Date: 2019-01-08
- Inventor: Shinichi Maeda
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2015-215001 20151030
- Main IPC: H01L21/8222
- IPC: H01L21/8222 ; H01L21/324 ; H01L27/082 ; H01L29/66 ; H01L29/732 ; H01L29/08

Abstract:
It is prevented that when a predetermined number of semiconductor chips having transistors are manufactured from one semiconductor wafer, manufacturing cost of a semiconductor device is increased due to excess semiconductor chips manufactured from the semiconductor wafer. A first bipolar transistor including a first emitter region having a first area is formed in a first chip formation region in an exposure region that can be exposed by one exposure step, and a second bipolar transistor including a second emitter region having a second area different from the first area is formed in a second chip formation region in the exposure region.
Public/Granted literature
- US20170338155A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2017-11-23
Information query
IPC分类: