Invention Grant
- Patent Title: Method for making three dimensional complementary metal oxide semiconductor carbon nanotube thin film transistor circuit
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Application No.: US15145733Application Date: 2016-05-03
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Publication No.: US10177199B2Publication Date: 2019-01-08
- Inventor: Yu-Dan Zhao , Qun-Qing Li , Xiao-Yang Xiao , Guan-Hong Li , Yuan-Hao Jin , Shou-Shan Fan
- Applicant: Tsinghua University , HON HAI PRECISION INDUSTRY CO., LTD.
- Applicant Address: CN Beijing TW New Taipei
- Assignee: Tsinghua University,HON HAI PRECISION INDUSTRY CO., LTD.
- Current Assignee: Tsinghua University,HON HAI PRECISION INDUSTRY CO., LTD.
- Current Assignee Address: CN Beijing TW New Taipei
- Agency: ScienBiziP, P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/84 ; H01L27/28 ; H01L51/00 ; H01L51/05 ; H01L51/10

Abstract:
A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.
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