A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.