An apparatus having an interface and a circuit is disclosed. The interface may be connectable to a plurality of counters and a plurality of pipelines. The circuit may be configured to increment the counters associated with a first data unit in response to the first data unit being available in a buffer, and monitor a plurality of decrements of the counters by the pipelines. Each pipeline may decrement a respective counter when finished with the first data unit in the buffer. The circuit may also be configured to block the pipelines from processing a second data unit in the buffer until all of the counters associated with the first data unit have been decremented.