Invention Grant
- Patent Title: Memory cell of static random access memory based on resistance hardening
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Application No.: US15550898Application Date: 2015-03-27
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Publication No.: US10192612B2Publication Date: 2019-01-29
- Inventor: Jingqiu Wang , Li Liu , Liang Chen
- Applicant: Institute of Automation Chinese Academy of Sciences
- Applicant Address: CN Beijing
- Assignee: Institute of Automation Chinese Academy of Sciences
- Current Assignee: Institute of Automation Chinese Academy of Sciences
- Current Assignee Address: CN Beijing
- Agency: Howard IP Law, PLLC
- Agent Jeremy Howard
- International Application: PCT/CN2015/075321 WO 20150327
- International Announcement: WO2016/154826 WO 20161006
- Main IPC: G11C11/417
- IPC: G11C11/417 ; G11C11/413 ; G11C11/412

Abstract:
The present invention provides a memory cell of a static random access memory based on resistance reinforcement, which includes a latch circuit and a bit selection circuit. The latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network. The bit selection circuit consists of NMOS transistors N5 and N6. The latch circuit form four storage nodes X1, X1B, X2, X2B. Compared to the conventional memory cell of a 6T structure, a resistance-capacitance network is added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset at a cost of increasing a small amount of area, thus ensuring correctness of data.
Public/Granted literature
- US20180025774A1 Memory Cell of Static Random Access Memory Based on Resistance Hardening Public/Granted day:2018-01-25
Information query
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